The present invention relates generally to integrated circuits including switched capacitor circuits, and more particularly to circuits and methods for reducing charge injection and clock feed-through in switched capacitor circuits.
An increasing number of modern analog and mixed-signal integrated circuits, such as analog-to-digital converters, digital-to-analog converters, sample-and-hold circuits, and analog filters, use switched capacitor circuits as basic building blocks. The continued demand for improved performance of such analog and mixed-signal circuits has resulted in more stringent requirements for the switched capacitor circuits.
Two fundamental problems which often limit the achievable precision in switched capacitor circuits are the charge injection and clock feed-through mechanisms associated with the turning off of metal-oxide-semiconductor (MOS) transistor switch elements in the switched capacitor circuits. Both charge injection and clock feed-through mechanisms introduce unwanted charges into nodes of switched capacitor circuits. These unwanted charges have the particularly detrimental effects of causing erroneous voltages to appear at high impedance circuit nodes. FIG. 1 shows an N-channel MOS field effect transistor having a source S and drain D, and also a gate G receiving a clock pulse CK. FIG. 2 shows a conventional CMOS transmission gate including an N-channel transistor M1 and a P-channel transistor M2 having its gate coupled to receive the logical complement of clock pulse CK. MOS transistors and CMOS transmission gates are commonly used in switched capacitor circuits, and are subject to clock feed-through and charge injection. “Clock feed-through” and “charge injection” are two separate mechanisms which cause an error voltage in switched capacitor circuits. While both of these mechanisms cause an error at the same time (on falling clock edges for N-channel transistors and on rising clock edges for P-channel transistors), they are unrelated in the sense that one mechanism does not cause the other. The error due to “clock feed-through” arises specifically from the gate overlap capacitances while the error from “charge injection” arises specifically from the charge that is stored in the channel area of a turned-on MOS transistor. When the MOS transistor turns off, this stored channel charge leaves the channel area and is “injected” into the source and drain terminals. To avoid confusion, the error due to “clock feed-through” is generally not referred to as “charge injection” as this term is reserved for the channel charge being “injected” to source/drain terminals.
There has been a great deal of effort to minimize the effects of charge injection from MOS switches in switched capacitor circuits, by using various known compensation schemes. The known charge injection compensation schemes aim to compensate for the charges injected into critical circuit nodes after the charges have been injected by the turning off of MOS switches. FIG. 3 shows a switched capacitor circuit used in a known technique for compensating for charge injection, described in U.S. Pat. No. 5,479,121 entitled “Compensating Circuit for MOSFET Analog Switches” issued Dec. 26, 1995 to Shen et al.
A first source of the error in a MOS transistor used as a switch in a switched capacitor circuit is the above mentioned channel charge that is “injected” into the source and drain electrodes when the transistor turns off. The fraction of the channel charge that flows to the source and drain depends on the source and drain impedances and also on the transition time of the clock signal CK which turns the transistor off.
A second source of the error in an MOS transistor switch is “clock feed-through” caused by gate-source and gate-drain overlap capacitances of the transistor. The overlap capacitance is directly proportional to the width W of the channel of the transistor. As the clock CK undergoes a transition which turns off the MOS transistor, the gate-source overlap capacitance causes the charge stored on a capacitor connected to the source electrode to change, and therefore cause a voltage change across the capacitor. The voltage change is referred to as “clock feed-through”.
FIGS. 4A and 4B show another circuit and associated timing diagram used to compensate for charge injection, described in U.S. Pat. No. 6,850,098 entitled “Method for Nulling Charge Injection in Switched Networks” issued Feb. 1, 2005 to Lee et al. The known charge injection compensation schemes have a number of disadvantages compared to the invention subsequently described herein. For example, the circuit of FIG. 4A relies on matching of switches S1, S2, and S3 as well as on matching capacitors C2 and C3. In the prior art circuit of FIG. 4A, the compensating switches S2 and S3 are turned on during the “nulling phase” while the critical switch S1 is turned off. Any mismatch in the three switches and any mismatch in the two capacitors will impair the ability of this circuit to effectively cancel the charge injection and clock feed-through. Typically the switches are relatively small devices and that means that they cannot be matched very well. The most notable disadvantages limiting the practicality of known charge injection compensation schemes include (1) relatively large integrated circuit chip layout area required for implementation, (2) increased circuit layout complexity which results in sub-optimal chip layout configurations, (3) the need to rely on matching of compensating switches and/or compensating capacitors for effective charge injection compensation, (4) inability to compensate charge injection in certain circuit topologies and limited ability to compensate charge injection in the other circuit topologies, (5) inability to reduce mismatches in charge injection into differential circuit nodes, and (6) introduction of additional capacitive loading to operational amplifiers used within switched capacitor circuits, resulting in increased power dissipation of the operational amplifiers.
Thus, there is an unmet need for a practical circuit and technique for significantly reducing both charge injection and clock feed-through in switched capacitor integrated circuits.
There also is an unmet need for a practical circuit and technique for significantly reducing charge injection mismatches and mismatches in clock feed-through.
There also is an unmet need for a circuit and technique for significantly reducing both charge injection and clock feed-through in switched capacitor integrated circuits that is very simple to implement and that occupies very small amount of chip layout area.
There also is an unmet need for a practical circuit and technique for significantly reducing both charge injection and clock feed-through in switched capacitor integrated circuits which requires very low power dissipation and which occupies very small amount of chip layout area.
There also is an unmet need for a practical circuit and technique for significantly reducing both charge injection and clock feed-through in switched capacitor integrated circuits which requires very low power dissipation and which does not rely on component matching.